RISC-V processor
a piplined processor implementation of RV32IM version RISC-V ISA using Verilog.
Source code repo
This is a hardware project built using Verilog HDL. It is a complete processor that supports the RV32IM version of RISC-V ISA. The proccessor is piplined to increase the throughput. It also supports the M extension for multiplication and divisoin. For more information regarding RISC-V RSA, check their specification or their website